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JBE, vol. 26, no. 2, pp.167-174, March, 2021

DOI: https://doi.org/10.5909/JBE.2021.26.2.167

Deep Learning-based Real-Time Super-Resolution Architecture Design

Saehyun Ahn and Suk-Ju Kang

C.A E-mail: sjkang@sogang.ac.kr

Abstract:

Recently, deep learning technology is widely used in various computer vision applications, such as object recognition, classification, and image generation. In particular, the deep learning-based super-resolution has been gaining significant performance improvement. Fast super-resolution convolutional neural network (FSRCNN) is a well-known model as a deep learning-based super-resolution algorithm that output image is generated by a deconvolutional layer. In this paper, we propose an FPGA-based convolutional neural networks accelerator that considers parallel computing efficiency. In addition, the proposed method proposes Optimal-FSRCNN, which is modified the structure of FSRCNN. The number of multipliers is compressed by 3.47 times compared to FSRCNN. Moreover, PSNR has similar performance to FSRCNN. We developed a real-time image processing technology that implements on FPGA.



Keyword: hardware accelerator, super-resolution, FPGA, deep learning

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